Active Mode Subclock Power Gating

作者：Mistry Jatin N^*; Myers James; Al Hashimi Bashir M; Flynn David; Biggs John; Merrett Geoff V

来源：IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014, 22(9): 1898-1908.

DOI：10.1109/TVLSI.2013.2280886

• Active mode
• embedded microprocessors
• energy harvesting
• leakage control
• low power
• power gating
• subthreshold

This paper presents a technique, called subclock power gating, for reducing leakage power during the active mode in low performance, energy-constrained applications. The proposed technique achieves power reduction through two mechanisms: 1) power gating the combinational logic within the clock period (subclock) and 2) reducing the virtual supply to less than V-th rather than shutting down completely as is the case in conventional power gating. To achieve this reduced voltage, a pair of nMOS and pMOS transistors are used at the head and foot of the power gated logic for symmetric virtual rail clamping of the power and ground supplies. The subclock power gating technique has been validated by incorporating it with an ARM Cortex-M0 microprocessor, which was fabricated in a 65-nm process. Two sets of experiments are done: the first experimentally validates the functionality of the proposed technique in the fabricated test chip and the second investigates the utility of the proposed technique in example applications. Measured results from the fabricated chip show 27% power saving during the active mode for an example wireless sensor node application when compared with the same microprocessor without subclock power gating.

• 出版日期2014-9