A continuous time delta-sigma modulator with reduced clock jitter sensitivity through DSCR feedback

作者：Radjen Dejan^*; Andreani Pietro; Anderson Martin; Sundstrom Lars

来源：Analog Integrated Circuits and Signal Processing, 2013, 74(1): 21-31.

DOI：10.1007/s10470-012-9960-2

• Delta-sigma
• Clock jitter
• Continuous time
• Peak current
• Switched-capacitor-resistor

The performance of continuous time delta-sigma modulators is limited by their large sensitivity to feedback pulse-width variations caused by clock jitter in their feedback DACs. To mitigate that effect, a dual switched-capacitor-resistor feedback DAC technique is proposed. The architecture has the additional benefit of reducing the typically high switched-capacitor-resistor DAC output peak currents, resulting in reduced slew-rate requirements for the loop-filter integrators. The feedback technique has been implemented with a third order, 3-bit delta-sigma modulator for a low power radio receiver, in a 65 nm CMOS process, where it occupies an area of 0.17 mm(2). It achieves an SNDR of 70 dB over a 125 kHz bandwidth with an oversampling ratio of 16. The power consumption is 380 mu W from a 900 mV supply.

• 出版日期2013-1