Hundred femtosecond jitter measurement using dual-channel ADC with imprecise clock stimulus

作者：Cetin E^*; Kuyel T

来源：Electronics Letters, 2012, 48(24): 1525-U11.

DOI：10.1049/el.2012.2267

A power splitter, a delay line, a dual-channel 16-bit pipeline analogue-to-digital converter (ADC), and a low-cost clock synthesiser are used with digital signal processing techniques to measure cycle-to-cycle random jitter. The proposed setup is capable of measuring the jitter of a device under test (DUT), using an ADC clock that has an order of magnitude higher jitter than the DUT. Experimental results show that the average jitter reading of a low phase noise frequency synthesiser is 312 fs rms, with a 38 fs standard deviation between multiple readings. An imprecise clock source with 7.7 ps rms jitter is used to clock the ADCs to do this 312 fs measurement. The method is compared to a 33 GHz oscilloscope, a low-noise spectrum analyser, and a high performance signal source analyser (SSA). The results are much more accurate than both the oscilloscope and the spectrum analyser, and are reasonably close to the results of the SSA.

• 出版日期2012-11-22