A 250 KS/s, 0.8 V ultra low power successive approximation register ADC using a Dynamic rail-to-rail comparator

作者：Kobenge Sekedi B^*; Yang Huazhong

来源：IEICE Electronics Express, 2010, 7(4): 261-267.

DOI：10.1587/elex.7.261

• rail-to-rail comparator
• sample-and-hold
• digital-to-analog converter
• analog-to-digital converter

A low voltage low power successive approximation register (SAR) analog-to-digital converter (ADC) based on a novel rail-to-rail comparator is proposed in this paper. The power consumption of the comparator is significantly reduced through dynamic operation while the speed is augmented by using an efficient regenerative latch. No biasing circuits are needed and there are no floating nodes in the comparator throughout the conversion process. The digital-to-analog converter (DAC) is formed from a binary array of MIM capacitors. The 250 KS/s ADC implemented in a 0.18 mu m process consumes only 1.35 mu W of power at a supply voltage of 0.8 V.

• 出版日期2010-2-25
• 单位清华大学