A fast fault injection platform of multiple SEUs for SRAM-based FPGAs

作者：Zhang, Rongsheng; Xiao, Liyi^*; Li, Jie; Cao, Xuebing; Qi, Chunhua; Li, Jiaqiang; Wang, Mingjiang

来源：Microelectronics Reliability, 2018, 82: 147-152.

DOI：10.1016/j.microrel.2018.01.014

• SRAM-based FPGA
• Multiple SEUs
• Fault injection

In recent years, SRAM-based FPGA has been applied in space due to its high density and configurability. However, due to its high sensitivity to SEU, it is difficult to be applied in space. With the decrease of the feature size, SRAM-based FPGA becomes more sensitive to SEU. Therefore, how to evaluate the sensitivity to SEU of a design in FPGA is very important for the application in space. This paper presents a fast fault injection platform for SRAM-based FPGA, which can emulate accumulated multiple SEUs in SRAM-based FPGA to evaluate the sensitivity of the design in FPGA. This paper uses the internal injection through ICAP which is faster than the external injection. In order to speed up the fault injection flow, this paper improves the fault injection from three key points. The proposed fault injection platform can repair the accumulated SEUs automatically by itself after completing an injection flow which can ensure that the next fault injection is valid. The locations for injection are effective at every clock in order to speed up by designing an optimized address generator. A fault injection flow based on pipeline is proposed to speed up the fault injection. We show the sensitivity of ISCAS85 benchmark circuits configured in FPGA and validate the fault injection platform by comparing the error rate and resource utilization. We show the speed in one fault inject flow for the flow based on both pipeline and non-pipeline flow. The results indicate the proposed fault injection flow based on pipeline has a faster speed.

• 出版日期2018-3
• 单位哈尔滨工业大学