A 6-Gbps dual-mode digital clock and data recovery circuit in a 65-nm CMOS technology

作者：Jeon Min Ki; Yoo Changsik^*

来源：Analog Integrated Circuits and Signal Processing, 2015, 85(1): 209-215.

DOI：10.1007/s10470-015-0613-0

• Clock and data recovery (CDR)
• Phase locked loop (PLL)
• Digitally-controlled oscillator (DCO)

A 6-Gbps dual-mode digital clock and data recovery (CDR) circuit for both the mesochronous clocking system and the plesiochronous clocking system has been developed. Fabricated in a 65-nm CMOS technology, the prototype consumes 25.2 and 22.8-mW from 1.2-V supply and root-mean-square jitter of the recovered clock was measured to be 7.2 and 8.5-ps for 6-Gbps mesochronous system and plesiochronous system, respectively. For both operation modes, less than 10(-12) bit-error-rate was achieved with 2(7)-1 pseudo-random binary sequence pattern and active area of the implemented CDR circuit is 0.025-mm(2).

• 出版日期2015-10