A novel topology for modular frequency dividers with enhanced speed and power efficiency

作者：Farsiani Sirous^*; Sahafi Ali; Sobhi Jafar

来源：Analog Integrated Circuits and Signal Processing, 2015, 84(2): 161-171.

DOI：10.1007/s10470-015-0541-z

• Modular frequency divider
• Low-power
• High-speed
• True-single-phase-clock (TSPC)
• Extended-TSPC (E-TSPC)

In this paper, we introduce a new topology for modular frequency dividers which improves the speed and decreases the power consumption in true-single-phase-clock (TSPC) based dividers and enhances the speed in their Extended-TSPC (E-TSPC) based counterparts. Two dividers are designed in 0.18 A mu m TSMC CMOS technology with 1.8 V supply voltage, to examine the speed and power efficiency of proposed structure. Post-layout simulation results reveal that in TSPC based design, use of proposed structure leads to about 38 % power reduction compared to the conventional topology. In addition, the E-TSPC based design achieves the speed as high as static dividers with maintaining the programmability and modularity of divider.

• 出版日期2015-8