A 1.4xFO4 self-clocked asynchronous serial link in 0.18 mu m for intrachip communication

作者：Zhang Y^*; Dobkin R^*; Unikovski A; Nahmanny D; Samuel G; Moyal M; Ginosar R^*

来源：Integration, the VLSI Journal, 2017, 59: 190-197.

DOI：10.1016/j.vlsi.2017.06.007

• On-chip interconnect
• Serial links
• Current-mode receiver
• Asynchronous circuits

In this paper, we describe a repeater-free asynchronous serial link architecture targeting 1 x FO4 bit time for on chip communication. Non-Return To Zero (NRZ) Data/Strobe code is used in the channel to achieve the target speed. Timing pulse trains are generated locally and are employed to drive high speed 'transition latches' in the serializer and deserializer. A RLC line model is derived by the HFSS electromagnetic solver. Inverter-based transmitters and receivers are found to perform faster than other circuits. A prototype device having 30 links and fabricated in Tower Semiconductor 0.18 mu m CMOS process is described. Measurement results show 3.73 Gb/s data rate over 6.1 mm wire interconnect, corresponding to 1.44xFO4 bit time.

• 出版日期2017-9