摘要

This paper introduces different classes of analog-to-digital converter (ADC) architecture that non-uniformly samples the analog input and shifts from conventional voltage quantization to a hybrid quantization paradigm wherein both voltage and time quantization are utilized. In this architecture, the sampling rate adapts to the input frequency, which maintains an alias-free spectrum and enables an anti-aliasing (AA) filtering in the digital domain to relax the analog AA filter. In addition, the digital AA filter can generate uniform outputs from non-uniform samples to interact with the synchronous digital signal processor seamlessly and benefit from reconfigurability and technology scaling. To prove the concept, a flash-based non-uniform sampling ADC is proposed and the circuit non-idealities of key building blocks are analyzed. A silicon prototype is implemented in a 65-nm CMOS, which utilizes a 15-level voltage quantizer and a shared time quantizer with maximum resolution of 9 ps. Combined with the digital AA filter, it improves SNR by 30 dB in comparison with a conventional 4-bit uniformly sampled Nyquist-rate ADC and measures an EVM of -28 dB for a 64 quadrature amplitude modulation input signal under a 30-dB higher blocker.

  • 出版日期2017-9