An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example

作者：Wang Yu Shun^*; Hsieh Min Han; Li James Chien Mo; Chen Charlie Chung Ping

来源：IEEE Transactions on Circuits and Systems I-Regular Papers, 2012, 59(8): 1644-1655.

DOI：10.1109/TCSI.2012.2206503

• Adder
• at-speed
• DLL
• LFSR
• PET
• single stack-at fault
• speed binning
• transition fault

This work presents the first case of using the pseudoexhaustive testing (PET) for high-speed high-order (> 32-bit) adders. It is shown that all single stack-at faults are detected by a pseudoexhaustive test set of 54 K patterns, compared to patterns in the past. Also, all transition faults are detected by a pseudoexhaustive test set of 13 M patterns, compared to 2(26x4) patterns in the past. In addition, with a programmable-delay clock generated from DLL, the adder latency is accurately measured. The proposed technique was validated by an example of a 6.4-GHz domino adder with 181 ps latency in a 90-nm CMOS technology. With the latency measurement, speed binning of high performance CPUs is now possible.

• 出版日期2012-8
• 单位中国科学院电工研究所