A design of wide input range triple-mode active rectifier with peak efficiency of 94.2 % and maximum output power of 8 W for wireless power receiver in 0.18 A mu M BCD

作者：Park Young Jun; Park Hyung Gu; Lee Juri; Oh Seong Jin; Jang Jae Hyeong; Kim Sang Yun; Pu Young Gun; Hwang Keum Cheol; Yang Youngoo; Seo Munkyo; Lee Kang Yoon^*

来源：Analog Integrated Circuits and Signal Processing, 2016, 86(2): 255-265.

DOI：10.1007/s10470-015-0650-8

• Triple-mode active rectifier
• A4WP
• 6.78 MHz resonant frequency
• Efficiency
• Wireless power receiver

This paper presents a full-CMOS receiver for an A4WP application. Two schemes were used in the proposed synchronous rectifier to increase the efficiency of the rectifier. One scheme involves a limiting reverse current that senses the output load current by changing the half synchronous rectifier mode and full synchronous rectifier mode. Another scheme proposes a high efficiency active rectifier with a delay locked loop (DLL), which is a highly efficient receiver circuit intended for use in resonant wireless charging applications with a 6.78 MHz resonant frequency. Each metal-oxide-semiconductor field-effect transistor of the proposed rectifier uses an AC input voltage for the on/off operation. Concurrently, the DLL can compensate for the delay caused by the voltage limiter, level shifter, and gate driver, which leads to the removal of the reverse leakage current and maximizes the power efficiency. This chip is implemented using 0.18 mu m technology with an active area of around 2.3 mm x 1.5 mm. When the magnitude of the AC input voltage is 10 V, the maximum efficiency of the proposed rectifier is 94.2 %. The range of AC input voltages is 3-20 V.

• 出版日期2016-2