A 5-Bit 500-MS/s Asynchronous Digital Slope ADC With Two Comparators

作者：Shu, Yujun^*; Mei, Fengyi; Yu, Youling; Wu, Jiangfeng

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2018, 65(4): 426-430.

DOI：10.1109/TCSII.2017.2695720

• Asynchronous
• digital slope
• delay cell
• self-disable comparator
• continuous-time comparator
• strong-arm comparator

In this brief, we design a single-channel 5-bit 500-MS/s asynchronous digital slope analog-to-digital converter. It is implemented and simulated in SMIC 55-nm CMOS technology. The power supply is 1.2 V and the improved delay cells are used, which can shorten the delay time to 50 ps. In addition, a self-disabled continuous-time comparator is used to save power. A strong-arm comparator is used to resolve the most significant bit, so that we can reduce the number of delay cells and increase the sampling speed. The simulation result achieved a signal-to-noise and distortion ratio of 25.81 dB.

• 出版日期2018-4
• 单位同济大学