Design and implementation of counting networks

作者：Sklyarov Valery^*; Skliarova Iouliia

来源：Computing, 2015, 97(6): 557-577.

DOI：10.1007/s00607-013-0360-y

• Hamming weight counter/comparator
• Parallel circuits
• Performance analysis and design
• Pipeline
• FPGA

The paper describes Hamming weight counters/comparators built on counting networks that incorporate two distinctive and important features. The counting networks are composed of simple logic (core) elements with incrementally reducing numbers of elements from the inputs to the outputs. This feature provides the same performance as the best known sorting networks with radically reduced complexity. Compared to a competitive design based on parallel counters, the propagation delays of signals passing through data independent segments within the circuit are shortened, which allows faster pipelined implementations. Several types of counting networks are elaborated, namely pure combinational, partially sequential with reusable fragments, and pipelined. The correctness of the proposed concept and scalability of the networks are proven. Formal expressions to estimate the complexity and throughput of the network are given. Finally, the results of extensive experiments, evaluations and comparisons are reported that demonstrate that the solutions proposed offer better characteristics than the best known alternatives.

• 出版日期2015-6