A New Method of Crossbar Structure Placement in Chip Physical Design

作者：Wu, Zhaohui; Zhou, Xiaoyang; He, Sudong; Li, Bin

来源：Journal of South China University of Technology(Natural Science Edition), 2018, 46(8): 33-37 and 45.

DOI：10.3969/j.issn.1000-565X.2018.08.005

• Chip layout
• Clock frequency
• Cross-bar structures
• Physical design
• Placement and routing
• Placement methods
• Routing congestion
• Timing problem

When dealing with high performance chip physical design, the paths generated by crossbar will cause logic cluster together and lead to congestion or badly timing, and hencemake it difficult for placement and routing tools to obtain a satisfied result. In this paper, a new structural placement method is proposed to solve the routing congestion and the induced timing problem through inserting the buffer tree by fully considering the characteristics of the crossbar. The method is verified by an experiment on a sub-module which is composed of more than 1.3 million gates and has main clock frequency of 1.5GHz by using the Global Foundries 14nm process. The experimental results show that, after using the proposed structural placement, the crossbar module TNS (total negative slack) is decreased from -29.0ns to -1.7ns, the WNS (worst negative slack) is increased from -53ps to -38ps, the total DRC errors number is decreased from 7094 to 352 and the total net length of crossbar is decreased from 772076μm to 442066μm. Furthermore, other modules of the design have also considerable improvements, with an increasing of 18.37% on TNS and 76.50% on WNS.

• 出版日期2018-8-1
• 单位华南理工大学