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An 18.7mW 10-GHz Phase-Locked Loop Circuit in 0.13-mu m CMOS
Tseng I Wei
Wu Jen Ming
International Symposium on VLSI Design, Automation and Test, Taiwan, 2009-04-27 to 2009-04-30.
This paper presents a 10-GHz phase-locked loop (PLL) design with low power for high speed networking. A mixed design of Current Mode Logic (CML) and True Single Phase Clock (TSPC) logic is presented to reduce the power consumption of the frequency divider. With gain-boosting design in the charge pump leads to low jitter and low reference spur. An additional diversity of VCO by user body bias is proposed to improve KVCO. The PLL circuit is fabricated in TSMC 0.13 mu m RF CMOS process. The chip occupies 1.03 x 0.91 mm(2), draws less than 18.7mW from a 1.2V supply, and is -117.43dBc/Hz at an offset frequency of 1MHz from the carrier.
Phase-Locked Loop (PLL); gain boosting; current mode logic (CML); True Single Phase Clock (TSPC); frequency divider
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