Multiple-frequency digital phase-locked loop based on multiphase clock divider with constant pulse interval

作者：Yahara Mitsutoshi; Fujimoto Kuniaki; Kiyota Hideo

来源：Electronics and Communications in Japan, 2018, 101(7): 40-47.

DOI：10.1002/ecj.12085

• constant pulse interval
• multiphase clock
• multiple frequency
• PLL

In the mobile communication equipment, the clock generator for driving each system is required to have a fast pull-in time, multiple signals of constant pulse interval, synchronization range, low output jitter, and wide lock-in range characteristics. In this paper, multiple-frequency multiphase clock digital-controlled phased-locked loop (MC-DCPLL) is proposed. In this loop, the pulse width error of the multiplied output signal is a time within one phase difference of the multiphase clock regardless of the multiplication ratio. The output jitter in the steady state is always within one phase difference of the multiphase clock. Since it is a control method by dividing ratio changeable type, the lock-in range is extremely wide. Also, the initial pull-in time is always completed in one cycle of the input signal without being influenced by the multiplication ratio. It is clarified by theory and simulation that these characteristics can be obtained. From the above, the versatility of the proposed multiple-frequency MC-DCPLL is extremely high, and it can be expected to be used for clock sources, and so on, in various mobile communication equipment systems.

• 出版日期2018-7