A 0.45-0.7 V 1-6 Gb/s 0.29-0.58 pJ/b Source-Synchronous Transceiver Using Near-Threshold Operation

作者：Choi Woo Seok^*; Shu Guanghua; Talegaonkar Mrunmay; Liu Yubo; Wei Da; Benini Luca; Hanumolu Pavan Kumar

来源：IEEE Journal of Solid-State Circuits, 2018, 53(3): 884-895.

DOI：10.1109/JSSC.2017.2786716

• Low-power I/O
• multi-phase calibration
• near-threshold-voltage circuit design
• near-threshold-voltage phase-locked loop (PLL)
• source-synchronous transceiver

A low-power source-synchronous multi-Gb/s transceiver is presented. Supply voltage is aggressively scaled to reduce power, and the speed penalty resulting from low-voltage operation is overcome by multiplexing transmitter/receiver synchronized by low-rate multi-phase clocks. Phase spacing errors incurred by device mismatches are corrected using a self-calibration scheme. The proposed phase calibration method uses a single digital DLL to calibrate all the phases, which makes it insensitive to offsets in the calibrating DLL. Fabricated in a 65-nm CMOS process, energy efficiency and data rate of the prototype transceiver vary from 0.29 to 0.58 pJ/bit and 1 to 6 Gb/s, respectively, as the supply voltage changes from 0.45 to 0.7 V.

• 出版日期2018-3