Addressing Failure and Aging Degradation in MRAM/MeRAM-on-FDSOI Integration

作者：Cai, Hao; Wang, You; Naviner, Lirida Alves de Barros; Liu, Xinning; Shan, Weiwei; Yang, Jun^*; Zhao, Weisheng

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2019, 66(1): 239-250.

DOI：10.1109/TCSI.2018.2854277

• Fully depleted silicon-on-insulator (FDSOI)
• magnetic tunnel junction (MTJ)
• spin transfer torque magnetic random access memory (STT-MRAM)
• voltage-controlled magnetic anisotropy (VCMA)
• magnetoelectric random access memory (MeRAM)
• aging
• reliability
• variability

In this paper, we discuss the potential foundry announced integration of magnetic random access memory (MRAM) on fully depleted silicon-on-insulator (FDSOI). The spin transfer torque magnetic tunnel junction (STT-MTJ) and the next-generation voltage-controlled magnetic anisotropy MTJ are separately integrated into a 28-nm FDSOI process as the MRAM or magnetoelectric random access memory (MeRAM)on-FDSOI integration. Micromagnetic and electrical simulations are used to evaluate the performance of hybrid circuits. Circuit-level design strategies are explored that use FDSOI leverage and spin-device characteristic to realize writing and sensing power-delay efficiency, robust, and reliable performance in the one-transistor one-MTJ MRAM/MeRAM bit-cell and sensing circuits. Reliability issues are discussed. Process variation and aging resilience strategies, e.g., step-wise back-bias, flip-well re-configuration, and write assist, are proposed to address failure and aging degradation in the MRAM/MeRAM-on-FDSOI integration. A qualitative summary demonstrates that the MRAM/MeRAM-on-FDSOI integration offers attractive performance for future non-volatile CMOS integration.

• 出版日期2019-1
• 单位TELECOM ParisTech; 北京航空航天大学; 东南大学