A power-efficient 12-bit analog-to-digital converter with a novel constant-resistance CMOS input sampling switch

作者：Jing Xin^*; Zhuang Yiqi; Tang Hualian; Dai Li; Du Yongqian; Zhang Li; Duan Hongbo

来源：Chinese Journal of Semiconductors, 2014, 35(2): 025002.

DOI：10.1088/1674-4926/35/2/025002

• Analog to digital converters
• Analog-to-digital
• Differential nonlinearity
• Hybrid compensation
• Low-voltage
• op-amp sharing
• Pipeline analog-to-digital converters
• Spurious-free dynamic range

A power-efficient 12-bit 40-MS/s pipeline analog-to-digital converter (ADC) implemented in a 0.13 μm CMOS technology is presented. A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire input signal range, is used at the sample-and-hold front-end to enhance the dynamic performance of the pipelined ADC. By implementing with 2.5-bit-per-stage and a simplified amplifier sharing architecture between two successive pipeline stages, a very competitive power consumption and small die area can be achieved. Meanwhile, the substrate-biasing-effect attenuated T-type switches are introduced to reduce the crosstalk between the two opamp sharing successive stages. Moreover, a two-stage gain boosted recycling folded cascode (RFC) amplifier with hybrid frequency compensation is developed to further reduce the power consumption and maintain the ADC's performance simultaneously. The measured results imply that the ADC achieves a spurious-free dynamic range (SFDR) of 75.7 dB and a signal-to-noise-plus-distortion ratio (SNDR) of 62.74 dB with a 4.3 MHz input signal; the SNDR maintains over 58.25 dB for input signals up to 19.3MHz. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are -0.43 to +0.48 LSB and -1.62 to +1.89 LSB respectively. The prototype ADC consumes 28.4 mW under a 1.2-V nominal power supply and 40 MHz sampling rate, transferring to a figure-of-merit (FOM) of 0.63 pJ per conversion-step.

• 出版日期2014
• 单位西安电子科技大学