A 6-bit, 500-MS/s current-steering DAC in SiGe BiCMOS technology and considerations for SFDR performance

作者：Reddy Reeshen^*; Sinha Saurabh

来源：Microelectronics Journal, 2015, 46(4): 310-319.

DOI：10.1016/j.mejo.2015.02.001

• Digital-analogue conversion
• BiCMOS integrated circuits
• Dynamic range
• Analogue-digital integrated circuits
• Mixed analogue digital integrated circuits
• Wideband

This paper presents a six-bit current-steering digital-to-analogue converter (DAC), which optimises the spurious free dynamic range (SFDR) performance of high-speed binary weighted architectures by lowering current switch distortion and reducing the clock feedthrough effect. A novel current source cell is implemented that comprises heterojunction bipolar transistor current switches, negative-channel metal-oxide semiconductor (NMOS) cascade and NMOS current source to overcome distortion by specifically enhancing the SFDR for high-speed DACs. The DAC is implemented using silicon-germanium (SiGe) BiCMOS 130 nm technology and achieves a better than 21.96 dBc SFDR across the Nyquist band for a sampling rate of 500 MS/s with a core size of 0.1 mm(2) and dissipates just 4 mW compared to other BiCMOS DACs that achieve similar SFDR performance with higher output voltages, resulting in a much larger power dissipation.

• 出版日期2015-4