A compact, low-power-consumption 5-Gbps OEIC receiver without equalizer fabricated in 0.18-mu m CMOS technology

作者：Fan, Chen^*; Wang, Rong; Wang, Zhi-gong

来源：IEICE Electronics Express, 2017, 14(15): 20170679.

DOI：10.1587/elex.14.20170679

• fully integrated
• equalizer
• avalanche mode
• optoelectronic integrated circuit
• very-short-reach

A low-cost, compact 5-Gbps fully integrated CMOS optical receiver without equalizer is fabricated in this paper in a standard 0.18-mu m CMOS technology. The measured responsivity of the DNW-strip-SMPD operating in avalanche mode is 1.4 A/W, while the bandwidth is 2.9 GHz with 11.6 V reverse bias voltage. The application for 5-Gbps very-short-reach optoelectronic integrated circuit (OEIC) receiver with a bit-error rate <10(-12) at incident optical power of -4 dBm has been experimentally demonstrated. The core chip area of the OEIC receiver is 0.736 mm by 0.515 mm, and it consumes 96 mW from the 1.8 V supply. Our OEIC receiver has the smallest area and the lowest power consumption in the OEIC receivers reported so far fabricated in 0.18-mu m CMOS technology.

• 出版日期2017-4-25
• 单位东南大学