A FIR-Embedded Phase Interpolator Based Noise Filtering for Wide-Bandwidth Fractional-N PLL

作者：Jee Dong Woo^*; Suh Yunjae; Kim Byungsub; Park Hong June; Sim Jae Yoon

来源：IEEE Journal of Solid-State Circuits, 2013, 48(11): 2795-2804.

DOI：10.1109/JSSC.2013.2282620

• Delta-sigma modulation
• FIR filtering
• fractional-N PLL
• phase interpolator
• phase-locked loop (PLL)
• phase noise
• quantization noise

This paper presents a 1-GHz Delta Sigma fractional-N PLL with a noise-filtering scheme using a FIR-embedded phase interpolator. The proposed dual-referenced interpolation scheme compensates for systematic nonlinearity in circuit operation and increases immunity to mismatches in input seed phases. By multiple use of a dual-referenced interpolator, the phase interpolator realizes an embedded FIR filtering for the quantization noise from the Delta Sigma modulator. The implemented PLL in 0.13-mu m CMOS consumes 16.8 mW and shows a reduction of the phase noise by 34 dB. With 3.2-MHz-wide bandwidth, the proposed filtering technique achieves an in-band noise of -106 dBc at 100 kHz and an out-of-band noise of -107.5 dBc at 6 MHz.

• 出版日期2013-11