An integrated 8-12 GHz fractional-N frequency synthesizer in SiGe BiCMOS for satellite communications

作者：Herzel Frank^*; Osmany Sabbir A; Hu Kai; Schmalz Klaus; Jagdhold Ulrich; Scheytt J Christoph; Schrape Oliver; Winkler Wolfgang; Follmann Ruediger; Koether Dietmar; Kohl Thorsten; Kersten Olaf; Podrebersek Thomas; Heyer Heinz Volker; Winkler Frank

来源：Analog Integrated Circuits and Signal Processing, 2010, 65(1): 21-32.

DOI：10.1007/s10470-010-9454-z

• Phase-locked loop
• Satellite communication
• Phase noise
• SiGe
• BiCMOS
• PVT tolerance

We present an integrated fractional-N low-noise frequency synthesizer for satellite applications. By using two integrated VCOs and combining digital and analog tuning techniques, a PLL lock range from 8 to 12 GHz is achieved. Due to a small VCO line tuning gain and optimized charge pump output biasing, the phase noise is low and almost constant over the tuning range. All 16 sub-bands show a tuning range above 900 MHz each, allowing temperature compensation without sub-band switching. This makes the synthesizer robust against variations of the device parameters with process, supply voltage, temperature and aging. The measured phase noise is -87 dBc/Hz and -106 dBc/Hz at 10 kHz and 1 MHz offset, respectively. In integer-N mode, phase noise values down to -98 dBc/Hz at 10 kHz and -111 dBc/Hz at 1 MHz offset, respectively, were measured.

• 出版日期2010-10