A 15-Gb/s 0.5-mW/Gbps Two-Tap DFE Receiver With Far-End Crosstalk Cancellation

作者：Nazari Meisam Honarvar^*; Emami Neyestanak Azita

来源：IEEE Journal of Solid-State Circuits, 2012, 47(10): 2420-2432.

DOI：10.1109/JSSC.2012.2203870

• Decision feedback equalization (DFE)
• far-end crosstalk (FEXT)
• interconnects
• receiver
• speculative
• summation
• switched capacitor (SC)

This paper presents a low-power receiver with two-tap decision feedback equalization (DFE) and novel far-end crosstalk (FEXT) cancellation capability, implemented in a 45-nm SOI CMOS process. The receiver employs a half-rate speculative DFE architecture to allow for the use of low-power front-end circuitry and CMOS clock buffers. In the proposed architecture, a switched-capacitor sample-hold at the front-end is employed to perform DFE tap summation. This technique is generalized to implement taps of equalization. The receiver compensates the effect of crosstalk without making a decision on the received aggressor signal. Due to the low-power nature of the switched-capacitor front-end, the crosstalk cancellation is possible with only 33 mu W/Gbps/lane power overhead. The receiver was tested over channels with different levels of loss and coupling. The signaling rate with BER < 10(-12) was significantly increased with the use of DFE and crosstalk cancellation scheme for highly coupled and lossy PCB traces. The DFE receiver equalizes 15-Gb/s data over a channel with more than 14-dB loss while consuming about 7.5 mW from a 1.2-V supply. At lower data rates it equalizes channels with over 21-dB loss.

• 出版日期2012-10