An ultra-low power SAR ADC with voltage window technique

作者：Wang Zheng Feng; Ning Ning^*; Wu Shuang Yi; Du Ling; Jiang Min; Yan Xiao Yan; Wang Wei

来源：Acta Electronica Sinica, 2016, 44(1): 211-215.

DOI：10.3969/j.issn.0372-2112.2016.01.031

• Analog to digital converters
• Biomedical applications
• Signal to noise and distortion ratio
• Successive approximation register
• Successive approximation register analog-to-digital converter
• Total power consumption
• Ultra low power
• Voltage window

An ultra-low power successive approximation register analog-to-digital converter for biomedical application is proposed. Many ultra-low power design methods are utilized for its main modules. The digital-to-analog converter (DAC) employs a vcm-based and split capacitor array structure to cut down the total capacitance, so as the power consumption. Voltage window technique is used to decrease the power consumption of the comparator without sacrificing its accuracy. Furthermore, stack forcing and multi-Vt design approaches are used to reduce the leakage current under low frequency. The proposed SAR ADC is designed and simulated in 55 nm process. With 0.6 V power supply and 10 kS/s sampling rate, the ADC achieves a signal-to-noise-and-distortion-ratio (SNDR) of 73.3 dB. The total power consumption is 432 nW and the figure-of-merit (FOM) is 11.4 fJ/Conv.

• 出版日期2016
• 单位电子科技大学