科研之友
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摘要
The single-slope analog-to-digital converter (SS-ADC) is the most commonly used column-level ADC for high-speed industrial, complementary metal-oxide semiconductor (CMOS)-based X-ray image sensors because of its small chip area (the width of a pixel), its simple circuit structure, and its low power consumption. However, it generally has a long conversion time, so we propose an innovative design: a complimentary dual-slope ADC (CDS-ADC) that uses two opposite ramp signals instead of a single ramp to double the conversion speed. This CDS-ADC occupies only 15% more area than the original SS-ADC. A prototype 12-bit CDS-ADC and a 12-bit SS-ADC were fabricated using a 0.35-A mu m 1P 4M CMOS process. During comparison of the two, the measured maximum differential non-linearity (DNL) of the CDS-ADC was a 0.49 least significant bit (LSB), the maximum integral non-linearity (INL) was a 0.43 LSB, the effective number of bits (ENOB) was 9.18 bits, and the figure of merit (FOM) was 0.03 pJ/conversion. The total power consumption was 0.031 uW. The conversion time of the new CDS-ADC was half that of the SS-ADC. The proposed dual-slope concept can be extended to further multiply the conversion speed by using multiple pairs of dual-slope ramps.
- 出版日期2014-2
