A Versatile Data Cache for Trace Buffer Support

作者：Lai, Chun Hung^*; Yang, Yun Chung; Huang, Ing Jer

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2014, 61(11): 3145-3154.

DOI：10.1109/TCSI.2014.2334892

• Cache
• design for debug
• multi-purpose cache
• processor debug
• reconfigurable cache
• trace storage

Since the cache system has been a predominant part in modern SoC's and its capacity is sometimes larger than necessary for specific applications, it is desirable to enhance the role of the cache system to beyond its original purpose (performance improvement). In this paper we propose a versatile data cache, called DT (data/trace) cache, by making it to function simultaneously as a regular data cache and as a trace buffer for real time software debugging and monitoring. It is accomplished by modifying the cache organization such that a portion of the cache ways can be configured as a trace buffer during the run time. The trace buffer stores the trace produced by some trace generation hardware while the rest portion of the data cache keeps its original role. The trace can be dumped out using the existing cache write back circuitry. The integration of a DT cache with an instruction cache, an academic ARM7 processor and a trace generator has been accomplished at RTL level. The hardware overhead is very minor and does not impair the global critical path delay. For a 16 KB (8 ways, 512 lines, 8 words) DT cache with only 1 way as the trace buffer, it is capable of storing 12771 cycles of the program trace at the cost of merely 553 gates and slight increase in cache miss rate on the average. The experiments show that the DT cache is a highly cost-effective approach for real time on-chip trace buffering.

• 出版日期2014-11
• 单位中山大学