A low power CMOS compatible embedded EEPROM for passive RFID tag

作者：Lee Kyoung Su; Chun Jung Hoon; Kwon Kee Won^*

来源：Microelectronics Journal, 2010, 41(10): 662-668.

DOI：10.1016/j.mejo.2010.06.006

• Non-volatile memory
• RFID tag
• Low power
• EEPROM

A 512-bit low-voltage CMOS-compatible EEPROM is developed and embedded into a passive RFID tag chip using 0.18 mu m CMOS technology. The write voltage is halved by adopting a planar EEPROM cell structure. The wide Vth distribution of as-received memory cells is mitigated by an initial erase and further reduced by an in-situ regulated erase operation using negative feedback. Although over-programmed charges leak from the floating gates over several days, the remaining charges are retained without further loss. The 512-bit planar EEPROM occupies 0.018 mm(2) and consumes 14.5 and 370 mu W for read and write at 85 degrees C, respectively.

• 出版日期2010-10