A Low-Noise and Area-Efficient PWM-Delta Sigma ADC Using a Single-Slope Quantizer for CMOS Image Sensors

作者：Jo Yun Rae^*; Hong Seong Kwan; Kwon Oh Kyong

来源：IEEE Transactions on Electron Devices, 2016, 63(1): 168-173.

DOI：10.1109/TED.2015.2430846

• CMOS image sensor (CIS)
• column-parallel readout
• delta-sigma (Delta Sigma) analog-to-digital converter (ADC)
• single-slope (SS) quantizer

This paper proposes a multibit pulsewidth modulated (PWM) delta-sigma (Delta Sigma) analog-to-digital converter (ADC) using a single-slope (SS) quantizer for a CMOS image sensor (CIS). In the proposed ADC, the multibit Delta Sigma modulation is performed by converting the pulsewidth of the PWM signal into multibit data using an SS quantizer. This suppresses the random noise by the multisampling operation and reduces the area of the multibit Delta Sigma ADC by adding a ramp signal to a single-bit Delta Sigma ADC. The proposed ADC with 12-b resolution was fabricated using a 0.13-mu m CIS process with a pixel array which has a Bayer patterned color filter and an image format of 580 x 450 with a pixel size of 5 mu m x 5 mu m. The size of the test chip is 4 mm x 5 mm, including the area of the proposed channel ADC, which occupies only 10 mu m x 400 mu m per channel. The measured results show a random noise of 65 mu V and a dynamic range of 70.4 dB.

• 出版日期2016-1