Design Considerations for Interleaved ADCs

作者：Razavi Behzad^*

来源：IEEE Journal of Solid-State Circuits, 2013, 48(8): 1806-1817.

DOI：10.1109/JSSC.2013.2258814

• Background calibration
• flash analog-to-digital converters (ADCs)
• figure of merit
• image
• interleaving mismatches
• low-power ADCs
• pipelined ADCs
• SAR ADCs
• timing mismatch

Interleaving can relax the power-speed tradeoffs of analog-to-digital converters and reduce their metastability error rate while increasing the input capacitance. This paper quantifies the benefits and derives an upper bound on the performance by considering kT/C noise and slewing requirements of the circuit driving the system. A frequency-domain analysis of interleaved converters is also presented that sheds light on the corruption mechanisms due to interchannel mismatches. A background timing mismatch calibration technique is proposed and experimentally shown to reduce the image to -75 dB for input frequencies exceeding 500 MHz.

• 出版日期2013-8