Analysis of 65 nm technology grounded-gate NMOS for on-chip ESD protection applications

作者：Dong S^*; Du X; Han Y; Huo M; Cui Q; Huang D

来源：Electronics Letters, 2008, 44(19): 1129-1130.

DOI：10.1049/el:20081073

Because of its simple structure and snapback characteristics, the grounded-gate NMOS (GGNMOS) has been widely used as an electrostatic discharge (ESD) protection device. ESD performance of GGNMOS fabricated in the 65 nm CMOS process is investigated, and measurement results for the snapback behaviour, failure current I-t2, holding voltage, and trigger voltage of such advanced MOS devices are illustrated. The effects of four key GGNMOS parameters, channel length, finger number, drain-to-gate spacing and source-to-gate spacing on the ESD performance, are considered, and optimal MOS structures for robust ESD protection applications are suggested.

• 出版日期2008-9-11
• 单位浙江大学