All-digital PLL with Delta Sigma DLL embedded TDC

作者：Han Y^*; Lin D; Geng S; Xu N; Rhee W; Oh T Y; Wang Z

来源：Electronics Letters, 2013, 49(2): 93-U3.

DOI：10.1049/el.2012.3017

An all-digital PLL (ADPLL) which employs a Delta Sigma delay-locked loop (DLL) to achieve a PVT-insensitive time resolution of the time-to-digital converter (TDC) as well as noise-shaped dithering is implemented in 65 nm CMOS. Experimental results show that the proposed method can achieve spur reduction with slight degradation of in-band phase noise. The 1.8 GHz ADPLL consumes 14.3 mW, while the TDC with the Delta Sigma DLL consumes 2.1 mW.

• 出版日期2013-1-17
• 单位清华大学