Accumulator Based 3-Weight Pattern Generation

作者：Paschalis Antonis^*; Voyiatzis Ioannis; Gizopoulos Dimitris

来源：IEEE Transactions on Very Large Scale Integration Systems, 2012, 20(2): 357-361.

DOI：10.1109/TVLSI.2010.2102373

• Built-in self test (BIST)
• test per clock
• VLSI testing
• weighted test pattern generation

Weighted pseudorandom built-in self test (BIST) schemes have been utilized in order to drive down the number of vectors to achieve complete fault coverage in BIST applications. Weighted sets comprising three weights, namely 0, 1, and 0.5 have been successfully utilized so far for test pattern generation, since they result in both low testing time and low consumed power. In this paper an accumulator-based 3-weight test pattern generation scheme is presented; the proposed scheme generates set of patterns with weights 0, 0.5, and I. Since accumulators are commonly found in current VLSI chips, this scheme can be efficiently utilized to drive down the hardware of BIST pattern generation, as well. Comparisons with previously presented schemes indicate that the proposed scheme compares favorably with respect to the required hardware.

• 出版日期2012-2