A New Error Correction Circuit for Delay Locked Loops

作者：Maillard Pierre^*; Holman W Timothy; Loveless T Daniel; Massengill Lloyd W

来源：IEEE Transactions on Nuclear Science, 2013, 60(6): 4387-4393.

DOI：10.1109/TNS.2013.2288103

• Delay-locked loop
• mixed-signal circuits
• RHBD
• SETs
• single-event effects
• two-photon absorption

A new error correction circuit (ECC) for delay-locked loops (DLLs) using combinational logic and a "peeled" voltage-controlled delay line (VCDL) layout is proposed. The ECC can be used to mitigate missing output pulses due to single-event effects in scaled CMOS processes. The implementation of the ECC results in no significant area penalty or performance degradation of the DLL. Simulations at LETs up to MeV-cm(2)/mg show that the ECC mitigates missing pulses in DLLs fabricated at features sizes down to 40 nm and operating frequencies up to 1 GHz. In addition, any ion strike within the error correction logic components will have no significant impact on the DLL output signal. Emulated results obtained through an FPGA implementation of the ECC demonstrate the effectiveness and portability of the hardening technique.

• 出版日期2013-12