A LOW-VOLTAGE 5.4 GHz MONOLITHIC CASCODE LNA USING 0.18 um CMOS TECHNOLOGY

作者：Liu, Baohong^*; Mao, Junfa

来源：Microwave and Optical Technology Letters, 2011, 53(2): 386-389.

DOI：10.1002/mop.25733

• low-noise amplifier
• cascode topology
• low voltage
• CMOS

This article presents a low-voltage monolithic cascade LNA using 0.18-um CMOS technology. Different from the stacked threshold voltage supply topology of conventional cascode LNA, this cascode LNA is designed as two cascaded stages for low-voltage application. For the purpose of lowering the whole power dissipation while RF performances are not influenced, the current occupation is reduced by decreasing the channel width of the second NMOS. The whole circuit is implemented through TSMC 0.18-um CMOS technology. Measurement results show that it can get 10.7-dB gain and 2.6 dB NF at frequency of 5.4 GHz. The IIP3 is about -2.3 dBm. The supply voltage is only 0.7 V. and the whole power dissipation is 6.3 mW.

• 单位
  上海交通大学