A Low-Noise High-Dynamic-Range 17-b 1.3-Megapixel 30-fps CMOS Image Sensor With Column-Parallel Two-Stage Folding-Integration/Cyclic ADC

作者：Seo Min Woong^*; Sawamoto Takehide; Akahori Tomoyuki; Liu Zheng; Iida Tetsuya; Takasawa Taishi; Kosugi Tomohiko; Watanabe Takashi; Isobe Keigo; Kawahito Shoji

来源：IEEE Transactions on Electron Devices, 2012, 59(12): 3396-3400.

DOI：10.1109/TED.2012.2215871

• CMOS image sensor (CIS)
• column-parallel folding-integration/cyclic analog-to-digital (A/D) converter (ADC)
• digital correlated double sampling (CDS)
• high dynamic range (DR)
• low vertical fixed pattern noise (FPN) (vFPN)
• multiple sampling technique

A 1.3-megapixel CMOS image sensor (CIS) with digital correlated double sampling and 17-b column-parallel two-stage folding-integration/cyclic analog-to-digital converters (ADCs) is developed. The image sensor has 0.021-e(rms)(-) vertical fixed pattern noise, 1.2-e(rms)(-) pixel temporal noise, and 85.0-dB dynamic range using 32 samplings in the folding-integration ADC mode. Despite the large number of samplings (32 times), the prototype image sensor is demonstrated at the video rate operation of 30 Hz by the new architecture of the proposed ADCs and the high-performance peripheral logic (or digital) parts using low-voltage differential signaling circuit. The developed 17-b CIS has no visible quantization noise at very low light level of 0.01 lx because of high grayscale resolution where 1 LSB = 0.1 e(-). The implemented CIS using 0.18-mu m technology has the sensitivity of 20 V/lx . s and the pixel conversion gain of 82 mu V/e(-).

• 出版日期2012-12