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摘要
In this paper we discuss a novel storage scheme for simultaneous memory access in parallel turbo decoder. The new scheme borrows its idea from vertex coloring in graph theory. Compared to similar method which also uses un-natural order in storage[2], our scheme requires more memory blocks but allows a simpler configuration method when code length changes, which can be implemented on-chip. The major bottleneck of our scheme is interconnection [3] since it doesn't put any constraint on interleaver. However, experiment shows, for a moderate decoding throughput(40-50M bits/sec), the hardware cost is still affordable with 3GPP's interleaver[4], 5 iterations and 80-100MHz system clock.
- 出版日期2005
- 单位上海交通大学
