A high-speed unified hardware architecture for 128 and 256-bit security levels of AES and the SHA-3 candidate Grostl

作者：Rogawski Marcin^*; Gaj Kris; Homsirikamol Ekawat

来源：Microprocessors and Microsystems, 2013, 37(6-7): 572-582.

DOI：10.1016/j.micpro.2013.05.005

• SHA-3 competition
• Hardware architectures
• Grostl
• AES
• Resource sharing
• Pipelining
• Scheduling
• IPSec

One of the five final SHA-3 candidates, Grostl, has been inspired by the Advanced Encryption Standard. This unique feature can be exploited in a large variety of practical applications. In order to have a better picture of the Grostl-AES computational efficiency (high-level scheduling, internal pipelining, resource sharing, etc.), we designed a high-speed coprocessor for the Grostl-based HMAC and AES in the counter mode. This coprocessor offers high-speed computations of both authentication and encryption/decryption with relatively small penalty in terms of area and speed when compared to the authentication (original Grostl circuitry) functionality only. From our perspective, the main advantage of Grostl over other finalists is the fact that its hardware architecture naturally accommodates AES at the cost of a small area overhead.

• 出版日期2013-10