A FPGA CORE GENERATOR FOR EMBEDDED CLASSIFICATION SYSTEMS

作者：Anguita Davide^*; Carlino Luca; Ghio Alessandro; Ridella Sandro

来源：Journal of Circuits, Systems, and Computers, 2011, 20(2): 263-282.

DOI：10.1142/S0218126611007244

• Core generator
• pattern recognition
• machine learning
• Support Vector Machine
• field programmable gate array

We describe in this work a Core Generator for Pattern Recognition tasks. This tool is able to generate, according to user requirements, the hardware description of a digital architecture, which implements a Support Vector Machine, one of the current state-of-the-art algorithms for Pattern Recognition. The output of the Core Generator consists of a high-level language hardware core description, suitable to be mapped on a reconfigurable device, like a Field Programmable Gate Array (FPGA). As an example of the use of our tool, we compare different solutions, by targeting several reconfigurable devices, and implement the recognition part of a machine vision system for automotive applications.