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摘要
1.2 kV buried-grid vertical 4H-SiC JFET structures with normally-on (N-on) and normally-off (N-off) designs were investigated by simulation. The static and dynamic characteristics of the devices were determined over a wide range of current, voltage and gate drive conditions in the temperature range -50 degrees C to 250 degrees C. In this paper, the properties of the N-on designs with threshold voltages (V(th)) -50 and -10 V are compared with the properties of the N-off design (V(th) = 0). For constant V(th), on-resistance decreases and output current increases with increasing channel doping and decreasing channel width. Simulations show that an on-resistance lower than 2 m Omega cm(2) at 250 degrees C can be obtained provided the channel width is smaller than 1.5 and 0.5 mu m for N-on JFETs with V(th) = -50 V and V(th) = -10 V, respectively, and lower than 3 m Omega cm(2) provided the channel width is smaller than 0.3 mu m for the N-off JFET. At the same time, E(on) decreases and E(off) increases with increased channel doping concentration and reduced channel width. It is shown that E(on) decreases with increasing channel doping concentration due to the reduced channel resistance for the faster turn-on process. E(off) increases with increasing channel doping concentration due to the increase in gate-drain capacitance, C(GD).
- 出版日期2010-11
