A systematic approach for design of digit-serial signal processing architectures

作者：Parhi; Keshab K.

来源：IEEE Transactions on Circuits and Systems, 1991, 38(4): 358-375.

DOI：10.1109/31.75394

• Digit-Serial Signal Processing Architectures
• Two's Complement Adders
• Two's Complement Multipliers
• Unfolding Transformation

A systematic unfolding transformation technique for transforming bit-serial architectures into equivalent digit-serial ones is presented. The novel feature of the unfolding technique lies in the generation of functionally correct control circuits in the digit-serial architectures. For some applications bit-serial architectures may be too slow, and bit-parallel architectures may be faster than necessary and may require too much hardware. The desired sample rate in these applications can be achieved using the digit-serial approach, where multiple bits of a sample are processed in a single clock cycle. The number of bits processed in one clock cycle in the digit-serial systems is referred to as the digit size;the digit size can be any arbitrary integer (the digit size was restricted to be a divisor of wordlength in past ad hoc designs). Digit-serial implementation of two's complement adders and multipliers is described. Least-significant-bit-first bit-serial implementation of two's complement division, square-root, and compare-select operations are presented, and the corresponding digit-serial architectures for these operations are obtained using the unfolding algorithm. Unfolding of multiple-rate operations (such as interpolators and decimators) is also addressed.

• 出版日期1991