A novel approach to reduce leakage current in ULP SRAM

作者：Singh Sanjay Kumar^*; Kaushik Brajesh Kumar

来源：IETE Journal of Research, 2013, 59(6): 704-708.

DOI：10.4103/0377-2063.126968

• CR
• DIBL
• Data retention voltage
• PR
• System on chip
• Static noise margin
• Static random access memory
• VLSI

This research paper deals with Static Random Access Memory (SRAM) design opportunities for low power consumption. Initially, four leakage current components are reviewed. Subsequently, some leakage current reduction techniques are discussed for a 6T SRAM cell. Based upon the configurations, a double fingered latch is analyzed and compared with a single finger latch that exhibits significant reduction in sub threshold leakage current. In this paper, the reduction of sub threshold leakage currents are demonstrated up to 12160 nA for 64K byte memory.

• 出版日期2013-12