Analysis of trigger behavior of high voltage LDMOS under TLP and VFTLP stress

作者：Zhu Jing^*; Qian Qinsong; Sun Weifeng; Liu Siyang

来源：Chinese Journal of Semiconductors, 2010, 31(1).

DOI：10.1088/1674-4926/31/1/014003

• ESD protection devices
• High voltage
• Low voltages
• Metal-oxide-semiconductor transistor
• Parasitic capacitance
• Physical mechanism
• Physical model
• Power transistors
• TCAD simulation
• Transmission line pulsing
• Very fast transmission line pulsing

The physical mechanisms triggering electrostatic discharge (ESD) in high voltage LDMOS power transistors (> 160 V) under transmission line pulsing (TLP) and very fast transmission line pulsing (VFTLP) stress are investigated by TCAD simulations using a set of macroscopic physical models related to previous studies implemented in Sentaurus Device. Under VFTLP stress, it is observed that the triggering voltage of the high voltage LDMOS obviously increases, which is a unique phenomenon compared with the low voltage ESD protection devices like NMOS and SCR. The relationship between the triggering voltage increase and the parasitic capacitances is also analyzed in detail. A compact equivalent circuit schematic is presented according to the investigated phenomena. An improved structure to alleviate this effect is also proposed and confirmed by the experiments.

• 出版日期2010
• 单位东南大学