An Ultra-Low Power 1.7-2.7 GHz Fractional-N Sub-Sampling Digital Frequency Synthesizer and Modulator for IoT Applications in 40 nm CMOS

作者：Liu Yao Hong^*; van den Heuvel Johan; Kuramochi Takashi; Busze Benjamin; Mateman Paul; Chillara Vamshi Krishna; Wang Bindi; Staszewski Robert Bogdan; Philips Kathleen

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2017, 64(5): 1094-1105.

DOI：10.1109/TCSI.2016.2625462

• All-digital PLL
• digital-to-time converter
• fractional-N PLL
• low-power transceiver
• sub-sampling PLL
• time-to-digital converter
• Internet of Things
• LMS

This paper introduces an ultra-low power 1.7-2.7-GHz fractional-N sub-sampling digital PLL (SS-DPLL) for Internet-of-Things (IoT) applications targeting compliance with Bluetooth Low Energy (BLE) and IEEE802.15.4 standards. A snapshot time-to-digital converter (TDC) acts as a digital subsampler featuring an increased out-of-range gain and without any assistance from the traditional counting of DCO edges, thus further reducing power consumption. With a proposed DCO-divider phase rotation in the feedback path, the impact of the digital-to-time converter's (DTC's) non-linearity on the PLL is reduced and improves fractional spurs by at least 8 dB across BLE channels. Moreover, a "variable-preconditioned LMS" calibration algorithm is introduced to dynamically correct the DTC gain error with fractional frequency control word (FCW) down to 1/16384. Fabricated in 40 nm CMOS, the SS-DPLL achieves phase noise performance of -109 dBc/Hz at 1 MHz offset, while consuming a record-low power of 1.19 mW.

• 出版日期2017-5