Mapping Parallel FFT Algorithm onto SmartCell Coarse-Grained Reconfigurable Architecture

作者：Liang Cao^*; Huang Xinming

来源：IEICE - Transactions on Electronics, 2010, E93C(3): 407-415.

DOI：10.1587/transele.E93.C.407

• coarse-grained reconfigurable architecture
• parallel FFT
• energy efficiency
• ASIC
• FPGA
• DSP

Fast Fourier Transform (FFT) is an important algorithm in many digital signal processing applications, and it often requires parallel Implementation for high throughput In this paper we first present the Sinai-tall coarse-grained reconfigurable architecture targeted for stream processing A SmartCell prototype integrates 64 processing elements. configurable interconnections. and dedicated Instruction and data memories Into a single chip. which is able to provide high performance parallel processing while maintaining post-fabrication flexibility Subsequently. we present a parallel FFT architecture targeted for multi-core platforms computing systems This algorithm provides ant optimized data flow patient that reduces both communication and configuration overheads The proposed parallel FFT algorithm is then mapped onto the SmartCell prototype device Results show that the parallel FFT implemention on SmartCell is about 14 9 and 2 7 times faster than network-on-chip (NoC) and MorphoSys Implementations. respectively SmartCell also achieves the energy efficiency gains of 2 1 and 28 9 when compared with FPGA and DSP implementations

• 出版日期2010-3