SparseRC: Sparsity Preserving Model Reduction for RC Circuits with Many Terminals

作者：Ionutiu Roxana^*; Rommes Joost; Schilders Wil H A

来源：IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2011, 30(12): 1828-1841.

DOI：10.1109/TCAD.2011.2166075

• Circuit simulation
• graphs
• model reduction
• moment matching
• partitioning
• passivity
• sparsity
• synthesis

A novel model order reduction (MOR) method, SparseRC, for multiterminal RC circuits is proposed. Specifically tailored to systems with many terminals, SparseRC employs graph-partitioning and fill-in reducing orderings to improve sparsity during model reduction, while maintaining accuracy via moment matching. The reduced models are easily converted to their circuit representation. These contain much fewer nodes and circuit elements than otherwise obtained with conventional MOR techniques, allowing faster simulations at little accuracy loss.

• 出版日期2011-12