A parallel power amplifier with load impedance transformation for optimized low power performance

作者：Lee Geunyong^*; Lee Jongsoo

来源：IEICE Electronics Express, 2011, 8(12): 956-962.

DOI：10.1587/elex.8.956

• chain matching networks
• load impedance transformation
• low power efficiency and linearity
• parallel power amplifier
• WCDMA

This paper presents analytic expressions for T-type chain matching network synthesis of the power amplifier (PA) to enhance the performance at low output powers via a load impedance adjustment. Here, a parallel power amplifier for WCDMA B1 (1920-1980 MHz) based on an InGaP/GaAs hetero-junction bipolar transistor (HBT) is utilized, which has a fully integrated matching network on a printed circuit board (PCB). As a result, the power amplifier shows a 38.7% power added efficiency (PAE), and a -37 dBc adjacent channel leakage power ratio (ACLR) at 27.5 dBm output during high power mode operation, and 17.6% PAE with a 22mA quiescent current and a -40.7 dBc at a back-off output power of 17 dBm during low power mode.

• 出版日期2011-6-25