Low phase noise millimeter wave monolithic integrated phase locked-loop

作者：Tang Lu^*; Wang Zhigong; Qiu Yinghua; Xu Jian

来源：High Technology Letters, 2012, 18(3): 263-266.

DOI：10.3772/j.issn.1006-6748.2012.03.007

• Analog multipliers
• Center frequency
• Differential current
• Driving capability
• GaAs
• GaAs pseudomorphic high electron mobility transistors (pHEMT)
• Low phase noise
• Millimeter-wave band
• On chips
• Output buffer circuit
• Output phase
• Output signal
• Resonant tanks
• Root mean square jitter

A Monolithic integrated phase locked-loop (PLL) with a low phase noise is proposed in this paper. Several techniques are utilized to improve the performance of the PLL which works at the millimeter-wave band. The on-chip high-Q coplanar waveguides (CPWs) are utilized in the resonant tank and the differential current amplifier with a resonator is used to realize the VCO. In the output buffer circuit, several stages of cascaded source-followers connect and differential amplifiers are adopted to improve the driving capability of the PLL';s output signals. An improved analog multiplier topology is also used in the PD circuit to improve the gain of the PD. The proposed PLL is realized with a 0.2 μm GaAs pseudomorphic high electron mobility transistor (PHEMT) process. At 10 kHz offset from the center frequency, the measured output phase noise of the PLL output is only -88.83 dBc/Hz. The circuit exhibits a low root mean square (RMS) jitter of 1.68 ps.

• 出版日期2012
• 单位东南大学