Adaptive clock gating technique for low power IP core design in SoC

作者：Chang Xiao Tao^*; Zhang Ming Ming; Zhang Zhi Min; Han Yin He

来源：Chinese Journal of Computers, 2007, 30(5): 823-830.

• Adaptive clock gating (ACG)
• Dynamic power
• Intelligence property (IP) core
• Leakage power
• Low power design
• System on chip (SoC)

Clock gating is a well-known technique to reduce dynamic power. This paper analyses the disadvantages of many clock gating techniques and points out that they are obstacles in Sys-tem-on-Chip (SoC) design. Based on the analysis of IP core model and the programmable clock gating technique, an adaptive clock gating (ACG) technique which can be easily realized is introduced for low power IP core design. ACG can automatically turn on or turn off the IP clock to not only reduce dynamic power but also reduce leakage power with the power gating technique. The experimental results on some IP cores in a real SoC show an average of 62.2% dynamic power reduction and 70.9% leakage power reduction without performance degradation.

• 出版日期2007