A 1.0-V 6-b 40 MS/s time-domain flash ADC in 0.18 mu m CMOS

作者：Huang, Guanzhong^*; Lin, Pingfen

来源：Analog Integrated Circuits and Signal Processing, 2013, 77(2): 285-289.

DOI：10.1007/s10470-013-0167-y

• Flash analog-to-digital converter (ADC)
• Time-domain comparator
• Resistive averaging
• Technology scaling

This paper presents a 6-bit low power low supply voltage time-domain comparator. The conventional voltage comparison is moved to time-domain so as to remove pre-amplifier and latch, which enables its feasibility to low supply voltage. The voltage-to-time converter is realized by the proposed linear pulse-width-modulation. The set-up time of the D flip-flop determines the sampling rate of the converter. The resistive averaging relaxes the matching requirement of the parallel comparison cells. The total input capacitance is decreased to less than 40fF in this architecture. The above digital-intensive setting makes the analog-to-digital converter (ADC) benefit from technology scaling in both power consumption and sampling rate. The prototype ADC is fabricated in SMIC 0.18 mu m CMOS process. At 40 MS/s and 1.0-V supply, it consumes 540 mu W and achieves an effective-number-of-bit of 5.43, resulting in a figure-of-merit of 0.31 pJ/conversion-step and active area of 0.1 mm(2).

• 出版日期2013-11
• 单位北京工业大学